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version: 1.3 page: 1 of 28 doc. version: 1.3 total pages: 28 date :2006.01.11 note: the content of this specification is subject to changewithout prior notice. ? 2004au optronics all rights reserved, do not copy. model name:a024cn 00 v2 product specification 2.36 color tft-lcd module < > preliminary specification <> final specification www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 2of2 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. record of revision versionrevise datepagecontent 1aug/31/2004first draft 1.1nov/09/20044n0.8panel surface treatmentrevise ag to glare 21 revise viewing angle left min from 45 to 40 viewing angle right min from 45 to 40 24change e. packing form 25fig2 outline dimension of tft_lcd module(add fpc ul mark) 25notice for backlight design and assembly 1.2nov/23/200425fig2 outline dimension of tft_lcd module update 1.3jan/11/200625update outline dimension of tft_lcd module(revise fpc ul mark) www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 3of3 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. contents: a.physical specification ..................................................... p4 b.electrical specifications ................................................... p5 c.optical specifications ..................................................... p21 d.reliability test items ....................................................... p23 e.packing form ............................................................... p24 www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 4of4 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. a. physical specifications no.itemspecificationremark 1display resolution(dot) 480(w) 234(h) 2active area(mm) 48.0(w) 35.685(h) 3screen size(inch)2.36(diagonal) 4dot pitch(mm) 0.10 (w) 0.1525(h) 5color configurationr. g. b. delta 6overall dimension(mm) 52.9(w) 43.73(h) 1.54 (d) note 1 7weight(g)tbd 8panel surface treatmentglare,hard coating, lr(low reflection) note 1: refer to fig. 1 www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 5of5 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. b. electrical specifications 1.pin assignment (please note: the pin assignments are tentative, subject to change prior to pin nosymboli/odescriptionremark 1drvvopower transistor gate signal for the boost converter 2fbvimain boost regulator feedback input 3adj0ipll adjustment pin0 4adj1ipll adjustment pin1 5pvddppower supply for pll circuits (3.3v) 6ncdno connection 7pgndpground pin for pll circuits 8ncdno connection 9vaivideo r input signal 10vbivideo g input signal 11vcivideo b input signal 12scliserial communication clock input 13sdaiserial communication data input 14csbiserial communication chip select 15grbiglobal reset pin 16vsyncivertical sync input. negative polarity 17hsyncihorizontal sync input. negative polarity 18dfrpodigital frame polarity output signal 19agndcground pin for source driver 20ncdno connection 21vci_outcpower supply for source driver 22vccpsystem power (3.3v) 23ncdno connection 24gndpsystem ground 25c1+c 26c1-c 27c12+c 28c12-c 29c8+c 30c8-c power setting capacitor connect pin www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 6of6 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. pin nosymboli/odescriptionremark 31v3c 32c31+c 33c31-c power setting capacitor connect pin 34apoloframe polarity outputsignalfor panel vcom 35vcaccapol level supply 36vghcvgh turn on voltage 37vglcpower setting capacitor connect pin 38vgofflcvglturn off voltage 39vgoffhcvgl+vcom 40vcomriadjust vcom dc voltage illustration of i/o symbol i: input. o: output. vi:voltage input.vo: voltage output. p:power.c: capacitor pin. d: dummy. note1:pleaserefer to figure below for the definition of scanning direction. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 7of7 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 2. equivalent circuit of i/o pin no & pin nameschematics 1.drv 15.grb 3. absolute maximum ratings itemsymbolconditionmin.max.unitremark v cc gnd=0-0.55.v powervoltage av dd av ss =0-0.55.5v input signal voltage vcom-2.95.2v operating temperature topa070 ambient temperature storage temperature tstg-2580 ambient temperature 4. electrical characteristics a.typical operating conditions (gnd=pgnd=0v) itemsymbolmin.typ.max.unitremark vcc2.73.33.6v pvdd2.73.33.6v vgh11.51415v note1. vgl-13,5-12-11.5v note1. vgoff_l-13.5-12-11.5v note1. vgoff_h-9.1-6.4-5.7v note1. power supply vci_out4.855.5v note1. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 8of8 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. v ia 0.25.0 v iac 3 ac component v idc 2.5 dc component video signal amplitude (vr,vg,vb) vi_high4.8 note 2. h levelv oh vcc-0.4 output signal voltage l levelv ol gndgnd+0.4 h levelv ih 0.7v cc -v cc v input signal voltage l levelv il gnd-0.3v cc v h levelioh10ua output current l leveliol-10ua analog stand by current ist200uadclk is stopped v cac 4.45.65.8vp-pac component vcom v cdc 1.1vdc component note 1. these voltages (vgh,vgl,vgoffh,vgoffl,vci_out) are related to input voltage vcc. note 2. the r,g,bmaximuminput voltage can not higher than 4.8 volt. b. current consumption (gnd=avss=0v) parametersymbolconditionmin.typ.max.unitremark i cc v cc =3.3v-22.5m a i dd av dd =3.3v-1.52.0m a 5. ac timing a.ntsc: parametersymbolmin.typ.max.unit.remark clock periodtime t osc 94103114ns hsync periodtime t hs 61.563.565.5 u s vsync pulse width twvs1-260hs vsync to hsync timingtvshs0 ns note1 hsync to vsync timingthsvs0 ns vsync to stv input timetvs51724 hs ref to fig. 6 horizontal lines per field256262.5268linenote 2 b. pal: parametersymbolmin.typ.max.unit.remark clock periodtime t osc 94103114ns hsyncperiodtime t hs 626466us vsync pulse width twvs1-260hs vsync to hsync timingtvshs0nsnote1 hsync to vsync timingthsvs0ns vsync to stv input timetvs122431hsref to fig. 6 horizontal lines per field306312.5318linenote 2 www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 9of9 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. note 1: vsync and hsync both support rising edge or falling edge timing note 2: please don't use odd horizontal lines to drive lcd panel for both odd and even field simultaneously. c. horizontal timing: parametersymbolmin.typ.max.unit.remark hsync frequencyfhs-15.7k- hz hsync pulse width timetwhs544600tclk hsync to dfrp change time thsdfrp-40-tclk hsync to apol change time thsapol-40-tclk refer to figure 3. d. 3-wire serial communication ac timing parametersymbolmin.typ.max.unit serial clocktsck3001ns scl pulse dutytscw405060% csb hold timetcst120ns serial data setup timetist120ns serial data hold timetiht120ns serial clock high/lowtssw120ns chip select distinguishtcd1us csb to vsync timetcv1us refer to figure 5. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 10of10 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 6.the configuration of serial data at sda terminal is at below msb lsb d1 5 d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 addressxdata no.d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0descriptiondefault xxxxxxxxxx 000 xxxxxxxxxx 00 1 xxxxxxxxxx 0 1 0 r0 000 xxxxxxxxxx 1 00 select relationship between the inputs va, vb, vc and outputs r, g, b. xxxxxxxxx 000 0 up to down xxxxxxxxx 000 1 down to up xxxxxxxxx 00 0 0 right to left xxxxxxxxx 00 1 0 left to right xxxxxxxxx 0 0 00 in reset state xxxxxxxxx 0 1 00 normal xxxxxxxxx 0 000 in standby mode r1 001 xxxxxxxxx 1 000 normal xxxxxxxx 00000 xxxxxxxx 0000 1 xxxxxxxx 000 1 0 xxxxxxxx 00 1 00 xxxxxxxx 0 1 000 r2 010 xxxxxxxx 1 0000 set horizontalposition xxxxxxxx 00000 xxxxxxxx 0000 1 xxxxxxxx 000 1 0 xxxxxxxx 00 1 00 xxxxxxxx 0 1 000 r3 011 xxxxxxxx 1 0000 set verticalposition xxxxxxxxx 0 110 xxxxxxxxx 000 1 xxxxxxxxx 00 1 0 xxxxxxxxx 0 1 00 adjust the vcom ac level xxxxxxxxx 0 000 the apol polarity, the same as dfrp. r4 100 xxxxxxxxx 1 000 the apol polarity will be inverted. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 11of11 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 addressxdata descriptiondefault xxxxxxxxx 000 0 data format selected by d1. xxxxxxxxx 000 1 data format auto selection. xxxxxxxxx 00 0 0 ntsc xxxxxxxxx 00 1 0 pal xxxxxxxxx 0 0 00 normally display xxxxxxxxx 0 1 00 16:9 widedisplay xxxxxxxxx 0 000 hsync and vsync input positive polarity r5 101 xxxxxxxxx 1 000 hsync and vsync input negative polarity xxxxxxxx 0000 0 pwm control circuit is shut down. xxxxxxxx 0000 1 pwm circuit is working. xxxxxxxx 000 0 0 pll is working. xxxxxxxx 000 1 0 pll is disabled. xxxxxxxx 100 00 pll freq. selection: ntsc default (594 clk/line) r6 110 xxxxxxxx 011 00 pal default (616 clk/line) x =>don tcare. register detail description register r0 : control and switch the relationship between the inputs va, vb, vc and outputs r, g, b. this function is used to match different types of color filters. output (n=1 to 160) d2d1d0 rgb rgbodd line 000 gbreven line gbrodd line 001 brgeven line brgodd line 01x rgbeven line rgbodd line 100 brgeven line gbrodd line 101 rgbeven line brgodd line 11x gbreven line x =>regardless www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 12of12 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. register r1 : set the scan direction, reset, and standby mode. bitfunction d0up/down scan direction. 1 => down to up. 0 => up to down (default). d1left/right scan direction. 1 => left to right. (default) 0 =>right to left. d2 global reset pin, it should be connected to vcc in normal operation.if connected to gnd, the controller is in reset state, normally pulled high. d3 standbymode, active low. normally pulled high. default scan direction is below: www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 13of13 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. register r2 : set the horizontalposition adjustmenttiming. d4d3d2d1d0no.unit 00000default 00001+1 00010+2 00011+3 00100+4 00101+5 00110+6 00111+7 01000+8 01001+9 01010+10 01011+11 01100+12 01101+13 01110+14 01111+15 10000-16 10001-15 10010-14 10011-13 10100-12 10101-11 10110-10 10111-9 11000-8 11001-7 11010-6 11011-5 11100-4 11101-3 11110-2 11111-1 dclk www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 14of14 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. register r3 : set the vertical position adjustment timing. d4d3d2d1d0no.unit 00000default 00001+1 00010+2 00011+3 00100+4 00101+5 00110+6 00111+7 01000x 01001x 01010x 01011x 01100x 01101x 01110x 01111x 10000x 10001x 10010x 10011x 10100-12 10101-11 10110-10 10111-9 11000-8 11001-7 11010-6 11011-5 11100-4 11101-3 11110-2 11111-1 h www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 15of15 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. register r4 : d0~d2: adjust the vcom ac level. vcac level setting (unit: v) d2d1d0level 0004.4 0014.6 0104.8 0115.0 1005.2 1015.4 1105.6(default) 1115.8 d3: set the polarity of apol. ifd3=0,then the polarity of apol is the same as the polarity of dfrp. as below: if d3=1, then the polarity of apol is inverted. as below: d3 control apol are inverted or not, normally pulled low. 0 =>the apol polarity, the same as dfrp, is negative at the first line. 1 =>the apol polarity will be inverted. vcom ac www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 16of16 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. register r5 : in this register, the input format of ntsc/pal is setting here. it would be set by auto-selection of external setting. apart from this 4:3 mode to 16:9 mode is also setting be d2 bit. and the sync polarity could be set by positive and negative. bitfunction d0 data format auto selection pin, normally pulled high. 1 =>data format is auto selection. 0 =>data format is decided by d1. d1 data format selection pin, normally pulled low. 1 =>pal. 0 =>ntsc. d2 wide display format selection pin, normally pulled low. 1 =>16:9 wide display. 0 =>normally display. d3 horizontal and vertical sync edge selection, normally pulled low. 0 =>horizontal and vertical sync input. positive polarity. 1 => horizontal and vertical sync input. negative polarity. register r6 in this register, pll clock is generated by internal synchronize signal. and the pll frequency can be set to adjust 4:3 circle ratio. bitfunction d0 shut down pin for pwm control circuit, normally pulled low. 1 =>pwm control circuit is working normally.. 0 =>pwm control circuit is shut down.. d1 disable pll pin, normally pulled low. 1 =>pll is disabled and clk must be input externally. 0 =>clk is generatedby pll. d2,d3,d4 pll frequency selection. note 3. d4d3d2clk/linefreq.unitcondition 000610 9.607 001612 9.639 010614 9.670 011616 9.702 100594 (default) 9.355 101597 9.402 110598 9.418 111600 9.450 mhz hsync frequency 15.75khz note 3. ntsc default setting is 594. pal default setting is 616. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 17of17 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 7.16:9 wide display since the input signal is 240 valid lines. in order to keep 16:9 format, 1/4 lines will be cancelled on the input signal.so the valid lines is 240x0.75=180, apart from this method, we will also write the black data to tft. and the black lines are60lines where occupied on the up site and bottom site separately. from above figure,we know that when in black region, weturn on the 15 gate pulses once and then turn on the other 15 gate pulses once. in display region, we show 180 lines normally. last the black region will be showed and the method is the same as the first 30 lines. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 18of18 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 8. dc-dc converter circuit a024cn00 contains one high-power step-up dc-dc converter, and backplane drive circuitry for active matrix tft lcds.the output voltage of the main boost converter can be set from vcc to 22v with external resistors.a024cn00design also include aprecision0.6vreference voltage, fault detection,and logic shutdown. a .boost converter a024cn00main boost converter uses a boost pwm architecture to produce a positive regulated voltage,please refer to the below figures to see the block diagram. fig1 dc-dc converter block diagram in the internal architecture of dc-dc converter. the feedback voltage(vfb) will connect to the triangle waveform comparator,and generates the output signal (cp0) which determines the duty cycle for (fdc). fig 2 dc ck block diagram www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 19of19 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. to reduce the noise affect,cp0 willbeprocessed by de-bounce circuit.state-machine will generate the duty cycle by cp0 signal.in order tomake sure that vfb can reach default vref quickly, state-machine s is designed with discrete step by step function(please refer to fig 3).if cp0 is low, the duty cycle will work from 0% to83%with the maximum duty ratio to83%. fig 3 pwm control state diagram www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 20of20 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. 9.reference circuit fb drv adj0 adj1 pvdd pgnd vc va vb grb sda csb scl dfrp vsync hsync agnd gnd1 vcc c1- c12+ c8- c8+ c12- c31- c31+ apol vgoffl vgoffh vgl vcomr p g n d g n d 1 c74 1uf c75 1uf c73 1uf c80 1uf 3.3v pvdd vcc 3.3v c64 1uf c79 1uf c67 1uf vcc c71 1uf vcomr c78 1uf c65 1uf c68 1uf c72 1uf c1+ c83 470pf c82 47nf r67 100k r66 150k gled vled vcc r62 10k c81 10uf c76 4.7uf vgh vci_out c70 1uf v3 c69 22uf vcac c77 1uf j4 con40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 21of21 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. c. optical specification (note 1,note 2, note 3) itemsymbolconditionmin.typ.max.unitremark risetr -2030ms response time falltf =0 -3040ms note 4, 6 contrast ratiocr at optimized viewing angle 100150-note 5, 6 top10 -- bottom 30-- left40-- viewing angle right cr R 10 40-- deg . note 6, 7 transmissiony l =0 -7.3-%note 8 v-t curve: liquid crystal voltage (v) transmission min.typ.max. 90% 1.51.82 50% 2.22.52.8 10% 2.93.253.5 note 1. ambient temperature =25 . note 2. to be measured in the dark room. 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 01.151.522.533.544.5 vlc t r a n s m i s s i o n www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 22of22 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. note 3.to be measured on the center area of panel with a field angle of 1 by topcon luminance meter bm-7, after 10 minutes operation. note 4. definition of response time: the output signals of photo detector are measured when the input signals are changed from black to white (falling time) and from white to black (rising time), respectively. the response timeis defined as the time interval between the 10% and 90% of amplitudes. refer to figure as below. note 5. definition of contrast ratio: contrast ratio is calculated with the following formula. photo detector output when lcd is at white state photo detector output when lcd is at black state note 6. white vi=v i50 1.5v black vi=v i50 2.0v means that the analog input signal swings in phase with com signal. means that the analog input signal swingsout of phase with com signal. v i50 : the analog input voltage when transmission is 50% the 100% transmission is defined as the transmission of lcd panel when all the input terminals of module are electrically opened. note 7. definition of viewing angle: refer to figure as below. note 8. measured at the center area of the panel when all the input terminals of lcd panel are electrically opened without apcf (light enhancement film). s i g n a l ( r e l a t i v e v a l u e ) "black" tr tf "white" "white" 0% 10% 90% 100% contrast ratio (cr)= www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 23of23 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. d. reliability test items: no.test itemsconditionsremark 1high temperature storage ta= 80 240hrs 2low temperature storage ta=-25 240hrs 3high temperature operation ta= 60 240hrs 4low temperature operation ta= 0 240hrs 5high temperature and high humidity ta= 60 . 90% rh 240hrsoperation 6heat shock -25 ~80 /50 cycle@2hrs/cycle non-operation 7electrostatic discharge 200v,200pf(0 ), once for each terminal non-operation frequency range : 10~55hz stoke: 1.5mm sweep: 10~55hz~10hz 2 hoursfor each direction of x,y,z 8vibration (6 hours for total) jis c7021, a-10 condition a 9mechanical shock 100g . 6ms, x, y, z 3 times for each direction jis c7021, a-7 condition c 10vibration (with carton) random vibration: 0.015g 2 /hz from 5~200hz C 6db/octave from 200~500hz iec 68-34 11drop (with carton) height: 80cm 1 corner, 3 edges, 6 surfaces 12the copper s strength for fpc the strength is larger 0.7 kg/cm ipc tm650 13the film s strength for fpc the strength is larger 0.35 kg/cm ipc tm650 14flexibility for fpc 1.curved radius: 2mm 2.pulling force: 250g mit folm : diagram of test set up for folding endurance note: ta: ambient temperature. www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 24of24 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. e. packing form p a n e l e p e t a p e ( t a p e ( b a c k e p e + www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 25of25 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. . f i g . 2 o u t l i n e d i m e n s i o n o f t f t - l c d m o d u l e www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 26of26 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. fig.3 horizontal timing diagram fig. 4 input video signal www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 27of27 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. fig. 5 3 - wire programming function timing www.datasheet.co.kr datasheet pdf - http://www..net/
version: 1.3 page: 28of28 all rights strictly reserved. any portion of this prper shall not be reproduced, copied, or transformed to any other forms without permission from au optronics corp. vsync hsync stv in tvs 1 23 456 // 12131415161718 ntsc odd frame vsync hsync stv in tvs 1 23 4511 // 12131415161718 ntsc even frame vsync hsync stv in tvs 1 23 456 // 19202122232425 pal odd frame vsync hsync stv in tvs 1 23 4518 // 19202122232425 pal even frame fig.6vertical timing diagram www.datasheet.co.kr datasheet pdf - http://www..net/

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